Robust design of LV/LP low-distortion CMOS rail-to-rail input stages

被引：4
|
作者：
Lin, CH [1 ]
Ismail, M
Pimenta, T
机构：
[1] Ohio State Univ, Dept Elect Engn, Analog VLSI Lab, Columbus, OH 43210 USA
[2] Escola Fed Engn Itajuba, Itajuba, Brazil
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 1999年 / 21卷 / 02期
关键词：
robust; low voltage; rail-to-rail; constant-g(m) input stage; Maximum Current Selecting Circuit; Transconductance Equalizer Bias Circuit;
D O I：
10.1023/A:1008377925289
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Two robust CMOS rail-to-rail OpAmp input stages are presented for low voltage (less than or equal to 3 V) applications. The robust input stages are implemented using two recently reported universal approaches to achieve constant transconductance. Transconductance control circuit is also introduced to compensate for K-p, K-n mismatch of PMOS and NMOS differential pairs in the input stage. The input stages are designed for operation in the strong inversion and have a rail-to-rail common mode input voltage range. Compared with an OpAmp with simple complementary input pairs, a two stage rail-to-rail OpAmp design example exhibits lower total harmonic distortion (THD) levels over the entire common mode input voltage range.
引用
收藏
页码：153 / 162
页数：10
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