A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 μm CMOS

被引：101
|
作者：
Cao, Zhiheng [1 ]
Yan, Shouli [2 ]
Li, Yunchu [3 ]
机构：
[1] Qualcomm, San Diego, CA 92121 USA
[2] Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA
[3] Analog Devices Inc, Wilmington, MA 01887 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 03期
关键词：
Analog-to-digital conversion; CMOS analog integrated circuits; low-power electronics; switched-capacitor circuits;
D O I：
10.1109/JSSC.2008.2012329
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 1.25 GS/s 6b ADC is implemented in a 0.13 mu m digital CMOS process by time-interleaving two SAR ADCs with 2.5 GHz internal clock frequency that converts 6 bits in 3 cycles. 5.5b ENOB at 1.25 GS/s and 5.8b ENOB at I GS/s are achieved without any off-line calibration, error correction or post processing. The entire ADC consumes 32 mW at 1.25 GS/s including T/H and reference buffers, and occupies 0.09 mm(2).
引用
收藏
页码：862 / 873
页数：12
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