Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation

被引：3

作者：

Narayanan, Rajeev ^{[1
]}

Seghaier, Ibtissem ^{[2
]}

Zaki, Mohamed H. ^{[2
]}

Tahar, Sofiene ^{[2
]}

机构：

[1] SUNY Coll New Paltz, Dept Elect & Comp Engn, New Paltz, NY 12561 USA

[2] Concordia Univ, Dept Elect & Comp Engn, Montreal, PQ H3G 1M8, Canada

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2013年 / 21卷 / 10期

关键词：

Analog designs; noise; process variation; run-time verification; statistical techniques; stochastic differential equations;

D O I：

10.1109/TVLSI.2012.2219083

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Noise and process variation present a practical limit on the performance of analog circuits. This paper proposes a methodology for modeling and verification of analog designs in the presence of shot noise, thermal noise, and process variations. The idea is to use stochastic differential equations to model noise in additive and multiplicative form and then combine process variation due to 0.18 mu m technology in a statistical run-time verification environment. The efficiency of MonteCarlo and Bootstrap statistical techniques are compared for a Colpitts oscillator and a phase locked loop-based frequency synthesizer circuit.

引用

页码：1811 / 1822

页数：12

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