Ensuring Correctness of Analog Circuits in Presence of Noise and Process Variations Using Pattern Matching

被引:0
|
作者
Narayanan, Rajeev [1 ]
Zaki, Mohamed H. [1 ]
Tahar, Sofiene [1 ]
机构
[1] Concordia Univ, Dept Elect & Comp Engn, Montreal, PQ, Canada
关键词
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper relies on the longest closest subsequence (LCSS), a variant of the longest common subsequence (LCS), to account for noise and process variations inherited by analog circuits. The idea is to use stochastic differential equations (SDE) to model the design and integrate device variation due to the 0.18 mu m fabrication process in a MATLAB simulation environment. LCSS is used to find the longest and closest subsequence that matches with the subsequence of an ideal circuit. We illustrate the proposed approach on a Colpitts oscillator circuit. Advantages of the proposed methods are robustness and flexibility to account for wide range of variations.
引用
收藏
页码:1188 / 1191
页数:4
相关论文
共 50 条
  • [1] Formal Verification of Analog Circuits in the Presence of Noise and Process Variation
    Narayanan, Rajeev
    Akbarpour, Behzad
    Zaki, Mohamed H.
    Tahar, Sofiene
    Paulson, Lawrence C.
    [J]. 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010), 2010, : 1309 - 1312
  • [2] Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation
    Narayanan, Rajeev
    Seghaier, Ibtissem
    Zaki, Mohamed H.
    Tahar, Sofiene
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (10) : 1811 - 1822
  • [3] PATTERN-MATCHING IN PRESENCE OF VISUAL NOISE
    ARNOULT, MD
    PRICE, CW
    [J]. JOURNAL OF EXPERIMENTAL PSYCHOLOGY, 1961, 62 (04): : 372 - &
  • [4] Leakage minimization of digital circuits using gate sizing in the presence of process variations
    Bhardwaj, Sarvesh
    Vrudhula, Sarma
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, 27 (03) : 445 - 455
  • [5] Performance Bound Analysis of Analog Circuits Considering Process Variations
    Hao, Zhigang
    Tan, Sheldon X. -D.
    Shen, Ruijing
    Shi, Guoyong
    [J]. PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 310 - 315
  • [6] Statistical test development for analog circuits under high process variations
    Liu, Fang
    Ozev, Sule
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (08) : 1465 - 1477
  • [7] Performance Bound and Yield Analysis for Analog Circuits under Process Variations
    Liu, Xue-Xin
    Palma-Rodriguez, Adolfo Adair
    Rodriguez-Chavez, Santiago
    Tan, Sheldon X. -D.
    Tlelo-Cuautle, Esteban
    Cai, Yici
    [J]. 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2013, : 761 - 766
  • [8] Sparse Statistical Model Inference for Analog Circuits under Process Variations
    Zhang, Yan
    Sankaranarayanan, Sriram
    Somenzi, Fabio
    [J]. 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2014, : 449 - 454
  • [9] Analysis of power supply noise in the presence of process variations
    Ghanta, Praveen
    Vrudhula, Sarma
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 2007, 24 (03): : 256 - 266
  • [10] Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations
    Raji, Mohsen
    Ghavami, Behnam
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (01) : 247 - 260