FDSOI versus BULK CMOS at 28 nm node Which Technology for Ultra-Low Power Design?

被引：0

作者：

Makipaa, Jani ^{[1
]}

Billoint, Olivier ^{[2
]}

机构：

[1] Natl Res Ctr Finland, VTT, Espoo, Finland

[2] CEA, LETI, Grenoble, France

来源：

2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2013年

基金：

芬兰科学院;

关键词：

Minimum energy operation; FDSOI; BULK; bulk biasing; back plane biasing; sub-threshold operation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Compared to BULK CMOS, FDSOI (Fully-Depleted Silicon-On-Insulator) introduces an ultra-thin buried oxide (BOX) layer and a dopant-free channel, which provides better performance and enhances ultra-low power (ULP) operation. To investigate benefits of utilizing FDSOI for ULP design, FDSOI and BULK CMOS 28 nm nodes are compared by simulating a test circuit. Threshold voltage tuning by back-plane biasing (BPB) for FDSOI and bulk biasing (BB) for BULK is analyzed. Contours of constant energy with minimum energy points (MEPs) are shown as well as energy delay products (EDPs). Simulation results show that FDSOI forward BPB can be used effectively to control operating frequency, EDP and MEP operation. Implications of the results are discussed last to give an overview how FDSOI performance gain over BULK CMOS can support in ULP design.

引用

页码：554 / 557

页数：4

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