Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects

We assess the degradation of stacked Silicon Gate-All-Around (GAA) Nanowire (NW) nFETs in the full [V-G, V-D} bias space. We perform extensive characterization to separate the intrinsic (i.e. the various degradation modes) from extrinsic effects (i.e., parasitic FETs and source/drain series resistance). The modelling of the degradation includes various channel hot-carrier (CHC) modes as well as PBTI and allows an extrapolation to 10-years lifetime in the full bias space. Moreover, by extraction of the activation energies of each of the degradation modes, and by obtaining the thermal resistance by S-parameter measurements, we compensate for any self-heating-induced acceleration or deceleration during overstress. As a result, we obtain a fully intrinsic nGAA-NWFET lifetime map in the entire bias space.