Design and Optimization of Single Electron Transistor based 4-Bit Arithmetic and Logic Unit at Room Temperature Operation

Single electron transistor (SET) has been envisaged as a potential device to achieve high-end performance in deep sub-micron technologies. The paper innovatively presents a 4-bit ALU based on single electron transistor (SET). The proposed logic design model is encouragingly operational at room temperature. SET based ALU has been designed, simulated and optimized with incorporation of all the parameters in the feasible fabrication range. Design and optimization have been performed in hierarchical manner i.e. from basic cells (device or transistor level) to circuit level. Performance comparison between SET, MOS and hybrid SET-MOS based circuits has been evaluated. From the simulation results, it is investigated that ALU based on SET with optimized parameters is more efficient compared to its MOS counterpart. The percentage improvements in SET over CMOS based ALU design in power, delay and power-delay product are 65.4%, 79.7% and 92.9% respectively. These improvements in SET over hybrid SET-MOS based ALU are 0.6%, 33.7% and 33.8 % respectively. The analyses have been performed at 45nm technology node using Cadence EDA tool.