Efficient VLSI Huffman encoder implementation and its application in high rate serial data encoding

被引：1

作者：

Wei, Rongshan ^{[1
]}

Zhang, Xingang ^{[1
]}

机构：

[1] Fuzhou Univ, Coll Phys & Informat Engn, Fuzhou 350116, Fujian, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2017年 / 14卷 / 21期

基金：

中国国家自然科学基金;

关键词：

Huffman coding; VLSI; serial data encoding; ARCHITECTURES;

D O I：

10.1587/elex.14.20170976

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a new data structure element for constructing a Huffman tree, and a new algorithm is developed to improve the efficiency of Huffman coding by constructing the Huffman tree synchronously with the generation of codewords. The improved algorithm is adopted in a VLSI architecture for a Huffman encoder. The VLSI implementation is realized using the Verilog hardware description language and simulated by Modelsim. The proposed scheme achieves rapid coding speed with a gate count of 9.962 K using SMIC 0.18 micron standard library cells.

引用

页数：11

共 50 条

[1] DATA STRUCTURE OF HUFFMAN CODES AND ITS APPLICATION TO EFFICIENT ENCODING AND DECODING
TANAKA, H
[J]. IEEE TRANSACTIONS ON INFORMATION THEORY, 1987, 33 (01) : 154 - 156
[2] VLSI implementation of a modified efficient SPIHT encoder
Huang, Win-Bin
Su, Alvin W. Y.
Kuo, Yau-Hwang
[J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2006, E89A (12) : 3613 - 3622
[3] A High-Throughput VLSI Architecture Design of Canonical Huffman Encoder
Shao, Zhenyu
Di, Zhixiong
Feng, Quanyuan
Wu, Qiang
Fan, Yibo
Yu, Xulin
Wang, Wenqiang
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69 (01) : 209 - 213
[4] An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation
Pandey, J. G.
Gurawa, Aanchal
Nehra, Heena
Karmakar, A.
[J]. 2016 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURES, TECHNOLOGY AND APPLICATIONS (VLSI-SATA), 2016,
[5] An efficient VLSI architecture for rate disdortion optimization in AVS video encoder
Yin, Hai Bing
Lou, Xi Zhong
Xia, Zhe Lei
Gao, Wen
[J]. PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 2805 - +
[6] RTL Design and VLSI Implementation of an efficient Convolutional Encoder and Adaptive Viterbi Decoder
Suganya, G. S.
Kavya, G.
[J]. 2013 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2013, : 494 - 498
[7] High-throughput VLSI Design and Implementation of MQ-Encoder
Di, Zhi-Xiong
Shi, Jiang-Yi
Hao, Yue
Liu, Kai
Li, Yun-Song
Zhao, Zhe-Fei
Ma, Pei-Jun
[J]. 2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 559 - 561
[8] THE VLSI IMPLEMENTATION OF A REED-SOLOMON ENCODER USING BERLEKAMP BIT-SERIAL MULTIPLIER ALGORITHM
HSU, IS
REED, IS
TRUONG, TK
WANG, K
YEH, CS
DEUTSCH, LJ
[J]. IEEE TRANSACTIONS ON COMPUTERS, 1984, 33 (10) : 906 - 911
[9] A novel memory-efficient Huffman decoding algorithm and its implementation
Chung, KL
Lin, YK
[J]. SIGNAL PROCESSING, 1997, 62 (02) : 207 - 213
[10] VLSI implementation of low-power cost-efficient lossless ECG encoder design for wireless healthcare monitoring application
Chen, S. -L.
Wang, J. -G
[J]. ELECTRONICS LETTERS, 2013, 49 (02) : 91 - 92

← 1 2 3 4 5 →