Analysis of Sub-threshold Inverter and 6T SRAM Cell for Ultra-Low-Power Applications

Rapid growth in semiconductor technology extends its applications in the fields of space and communications extensively. VLSI circuits with increased functionality and reduced area is the key factor in the applications. Device scaling yields integration of more functionality, hence increases the portability. Device scaling causes more leakages, and hence wasting more power in the steady state, consequently battery life in those systems reduced very critically. In recent years, the signficant use of battery-operated devices leads to the importance of low-power circuit design. This motivates the design of ultra-low power VLSI circuits in the scaled devices. Reduced supply voltage VDD can minimize the energy per operation, active power and leakages, but which are affected by DIBL. And decreased VDD forces the device performance very slow, which causes to increase the power-delay product (PDP). To maintain lowest possible amount point of PDP, it is necessary to operate the devices in its sub-threshold region. In this work, we described the design procedure of sub-threshold inverter and 6T SRAM cell. We used Cadence Virtuoso tools and GPDK 45 nm technology files.