An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

被引：0

作者：

刘鸣 ^{[1
]}

陈虹 ^{[1
]}

李长猛 ^{[1
]}

王志华 ^{[1
]}

机构：

[1] Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics,Tsinghua University

来源：

Journal of Semiconductors | 2010年 / 31卷 / 06期

基金：

中国国家自然科学基金;

关键词：

sub-threshold SRAM; 11T SRAM cell; ultra-low-power SoC;

D O I：

暂无

中图分类号：

TN432 [场效应型];

学科分类号：

080903 ; 1401 ;

摘要：

This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure.Final test results verify the function of the SRAM.The minimal operating voltage of the chip is 350 mV,where the speed is 165 kHz,the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.

引用

页码：144 / 147

页数：4

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