Evaluation of Cu/Ni/SnAg Microbump Bonding Processes for Thin-chip-on-chip Package using a Wafer-level Underfill Film

被引:0
|
作者
Lee, Chang-Chun [1 ]
Yang, Tsung-Fu [2 ]
Kao, Kuo-Shu [3 ]
Cheng, Ren-Chin [3 ]
Zhan, Chau-Jie [3 ]
Chen, Tai-Hong [3 ]
机构
[1] Chung Yuan Christian Univ, Dept Mech Engn, 200 Chungpei Rd, Chungli 32023, Taoyuan County, Taiwan
[2] Topco Sci Co LTD, Elect Div, Business Grp 3, Chungli, Taoyuan County, Taiwan
[3] Ind Technol Res Inst 195 Sec 4, Elect & Optoelectron Res Labs, Assembly & Reliabil Technol Dept, Hsinchu 31040, Taiwan
关键词
Underfill bonding process; Microbumps; Warpage; FEA; 3D ICs; FLIP-CHIP;
D O I
暂无
中图分类号
O414.1 [热力学];
学科分类号
摘要
Three-dimension (3D) integration provides a promising approach to build complex microsystems through bonding and interconnection of individually optimized device layers without sacrificing system performance. The use of traditional underfill processes is expected to suffer an arduous challenge as the filled gap of a large scale chip is narrowed down to several micrometers. Consequently, the subsequent reliability of mirobump joints and the relative assembly compatibility of stacked chips of 3D integrated circuits (ICs) packages are therefore deteriorated. To resolve the foregoing critical issue, a novel technology of wafer-level underfill film (WLUF) is developed. The concerned steps like alignment of WLUF coated chip to substrate chip and voids elimination to make this technology work are demonstrated. However, the co-planarity of stacked thin chips after assembling with WLUF is an urgent problem and needs to understand in detail. For this reason, this research presents a non-linear finite element analysis (FEA) with process-oriented simulated technique to estimate the warpage of stacked thin chips. On account of experimental validation, the effects of several key designed factors on the thermo-mechanical behavior of chip-on-chip package under various bonding forces are investigated. The most important findings from analytic results indicate that with a consideration of chip thickness thinner than 50 mu m at the outermost region of packaging structure without microbumps, a about 2 mu m of gap betweens chips is significantly reduced. The above-mentioned phenomenon is attributed to a major structural support at the purlieus of chip only come from WLUF is extremely weak when a uniform bonding pressures is loaded. It is also found that the following cooling procedure of WLUF would further aggravate the warpage magnitude of stacked thin chips. All the results shown in the work could be as a guideline while the bonding reliability as well as the design of structural optimization for packaging assemblies with WLUF is further improved.
引用
收藏
页码:385 / 391
页数:7
相关论文
共 37 条
  • [31] Impact of Isothermal Aging and Sn Grain Orientation on the Long-Term Reliability of Wafer-Level Chip-Scale Package Sn-Ag-Cu Solder Interconnects
    Lee, Tae-Kyu
    Zhou, Bite
    Bieler, Thomas R.
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2012, 2 (03): : 496 - 501
  • [32] Microfabrication of ultrahigh density wafer-level thin film compliant interconnects for through-silicon-via based chip stacks (vol 24, pg 1780, 2006)
    Arunasalam, Parthiban
    Ackler, Harold D.
    Sammakia, Bahgat G.
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2007, 25 (01): : 292 - 292
  • [33] Study of Three-Dimensional Small Chip Stacking Using Low Cost Wafer-Level Micro-bump/B-Stage Adhesive Film Hybrid Bonding and Via-Last TSVs
    Yao, Mingjun
    Zhao, Ning
    Wang, Teng
    Yu, Daquan
    Xiao, Zhiyi
    Ma, Haitao
    JOURNAL OF ELECTRONIC MATERIALS, 2018, 47 (12) : 7544 - 7557
  • [34] Study of Three-Dimensional Small Chip Stacking Using Low Cost Wafer-Level Micro-bump/B-Stage Adhesive Film Hybrid Bonding and Via-Last TSVs
    Mingjun Yao
    Ning Zhao
    Teng Wang
    Daquan Yu
    Zhiyi Xiao
    Haitao Ma
    Journal of Electronic Materials, 2018, 47 : 7544 - 7557
  • [35] Optimization and Characterization of Low-Temperature Wafer-Level Hybrid Bonding Using Photopatternable Dry Film Adhesive and Symmetric Micro Cu Pillar Solder Bumps
    Yao, Mingjun
    Zhao, Ning
    Wang, Teng
    Yu, Daquan
    Xiao, Zhiyi
    Ma, Haitao
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2018, 8 (10): : 1855 - 1862
  • [36] Effect of phase separation on mechanical strength of co-sputtering Cu(Ti) thin film in chip-level 3DIC bonding
    Lin, Po Chen
    Chen, Hao
    Hsieh, Hsien-Chien
    Wu, Albert T.
    MATERIALS LETTERS, 2017, 189 : 93 - 96
  • [37] High-Q on-chip inductors using thin-film wafer level packaging technology demonstrated on a 90nm RF-CMOS 5GHz VCO
    Sun, X.
    Linten, D.
    Dupuis, O.
    Carchon, G.
    Soussan, P.
    Decoutere, S.
    De Raedt, W.
    35TH EUROPEAN MICROWAVE CONFERENCE, VOLS 1-3, CONFERENCE PROCEEDINGS, 2005, : 77 - 80