A Scalable HCI Reliability model for 40nm nMOSFET

被引：0

作者：

Zhang, Mengdi ^{[1
]}

Li, Xi ^{[1
]}

Wang, Mingjuan ^{[1
]}

Shi, Yanling ^{[1
]}

Ren, Zheng

Hu, Shaojian

机构：

[1] E China Normal Univ, Dept EE, Shanghai 200241, Peoples R China

来源：

ELECTRONIC INFORMATION AND ELECTRICAL ENGINEERING | 2012年 / 19卷

关键词：

hot carrier injection; reliability modeling; MOSRA; PSP model;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper introduces a scalable PSP model for hot carrier injection (HCI) in 40nm MOSFET. With proposed model parameters, MOSRA model can simulate devices of different channel size very well. Modeled electrical characteristics, including I-V curve, I-dlin, I-sat and V-thlin depending on stress time, show good consistency with measured performance. This proposed model provides an accurate and fast way for reliability modeling in deep sub-micron CMOS technology.

引用

页码：67 / 69

页数：3

共 50 条

[41] Lithography Aware Statistical Context Characterization of 40nm Logic Cells
Rubin, Mark E.
Kobayashi, Naohiro
Yanagihara, Toshiaki
DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION III, 2009, 7275
[42] 40nm技术大幅度提升FPGA性能
电子设计技术, 2008, (06) : 17 - 17
[43] Challenge for under 40nm size pattern making for EUV mask
Abe, Tsukasa
Inazuki, Yuichi
Kobayashi, Yukie
Morikawa, Yasutaka
Mohri, Hiroshi
Hayashi, Naoya
PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY XX, 2013, 8701
[44] Energy Efficency of Asynchronous and Synchronous VLSI Circuit on 40nm and 90nm FPGA
Pandey, Bishwajeet
Yadav, Jyotsana
Singh, Yogesh Kumar
Swarnkar, Pradip
2013 INTERNATIONAL CONFERENCE ON ENERGY EFFICIENT TECHNOLOGIES FOR SUSTAINABILITY (ICEETS), 2013,
[45] Hot Electron Source Side Injection Comprehension in 40nm eSTM™
Melul, Franck
Kempf, Thibault
della Marca, Vincenzo
Bocquet, Marc
Akbal, Madjid
Trenteseaux, Frederique
Mantelli, Marc
Regnier, Arnaud
Niel, Stephan
la Rosa, Francesco
2021 IEEE INTERNATIONAL MEMORY WORKSHOP (IMW), 2021, : 91 - 94
[46] A Quad-core Coupled VCO in 40nm CMOS Technology
Zhou, Wei
Li, Qin
2018 INTERNATIONAL CONFERENCE ON MICROWAVE AND MILLIMETER WAVE TECHNOLOGY (ICMMT2018), 2018,
[47] 28V ESD clamp in CMOS 40nm process
Chowdary, G.
Neri, F.
Somajayula, S.
Notermans, G.
2012 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID STATE CIRCUIT (EDSSC), 2012,
[48] 40nm射频MOS器件性能及模型研究
刘林林
电子技术, 2021, 50 (07) : 11 - 13
[49] The Observation of Mobile Ion of 40nm node by Triangular Voltage Sweep
Huang, Clement
Liang, James W.
Juan, Alex
Su, K. C.
2014 IEEE 21ST INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2014, : 332 - 335
[50] SRAM VMIN Yield Challenge in 40nm Embedded NVM Process
Luo, L. Q.
Wang, D. X.
Zhang, F.
Tan, J. B.
Chow, Y. T.
Kong, Y. J.
Huang, J. Y.
Liu, Y. M.
Oh, M.
Balan, H.
Khoo, P.
Chen, C. Q.
Liu, B. H.
Shum, D.
Shubhakar, K.
Pey, K. L.
PROCEEDINGS OF THE 22ND INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2015), 2015, : 115 - 118

← 1 2 3 4 5 →