An Address Remapping Algorithm to Reduce Power Consumption in NoC-based Chip-Multiprocessors

NoC-based Chip-Multiprocessors(CMPs) are promising mechanisms which are essential to satisfy a growing need for easily scalable and high-performance in recent decades. However, in the process of running the programs, there are some data that misses from L1 cache to L2 cache. These cache misses have some effects on network congestion and access time. In this paper, we use the average number of hops to describe the fairness of the thread resources and explain each thread's access to each bank is fair. After then, we described an address remapping algorithm for cache miss in NoC-based CMPs. We evaluate our mechanism using Simplescalar and Cacti power simulation tool. Experimental results show that address remapping achieves significant improvement in the system performance and power consumption.