A nanophotonic interconnect for high-performance many-core computation

被引：41

作者：

Beausoleil, R. G. ^{[1
]}

Ahn, J. ^{[1
]}

Binkert, N. ^{[1
]}

Davis, A. ^{[1
]}

Fattal, D. ^{[1
]}

Fiorentino, M. ^{[1
]}

Jouppi, N. P. ^{[1
]}

McLaren, M. ^{[1
]}

Santori, C. M. ^{[1
]}

Schreiber, R. S. ^{[1
]}

Spillane, S. M. ^{[1
]}

Vantrease, D. ^{[1
]}

Xu, Q. ^{[1
]}

机构：

[1] HP Labs, Palo Alto, CA 94304 USA

来源：

16TH ANNUAL IEEE SYMPOSIUM ON HIGH-PERFORMANCE INTERCONNECTS, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/HOTI.2008.32

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Silicon nanophotonics holds the promise of revolutionizing computing by enabling parallel architectures that combine unprecedented performance and ease of use with affordable power consumption. Here we describe the results of a detailed multiyear design study of dense wavelength division multiplexing (DWDM) on-chip and off-chip interconnects and the device technologies that could improve computing performance by a factor of 20 above industry projections over the next decade.

引用

页码：182 / 189

页数：8

共 50 条

[1] A Nanophotonic Interconnect for High-Performance Many-Core Computation
Beausoleil, R. G.
Fiorentino, M.
Ahn, J.
Binkert, N.
Davis, A.
Fattal, D.
Jouppi, N. P.
McLaren, M.
Santori, C. M.
Schreiber, R. S.
Spillane, S. M.
Vantrease, D.
Xu, Q.
2008 5TH IEEE INTERNATIONAL CONFERENCE ON GROUP IV PHOTONICS, 2008, : 365 - 367
[2] High-Performance Intrusion Response Planning on Many-Core Architectures
Iannucci, Stefano
Chen, Qian
Abdelwahed, Sherif
2016 25TH INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS AND NETWORKS (ICCCN), 2016,
[3] Shenwei-26010: A High-Performance Many-Core Processor
Hu X.
Ke X.
Yin F.
Zhao X.
Ma Y.
Yan S.
Ma C.
Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2021, 58 (06): : 1155 - 1165
[4] High-Performance Cluster Estimation Using Many-Core Models
Seo, Junsang
Kang, Myeongsu
Kim, Cheol-Hong
Kim, Jong-Myon
FRONTIER AND INNOVATION IN FUTURE COMPUTING AND COMMUNICATIONS, 2014, 301 : 193 - 201
[5] Interconnect Network Analysis of Many-Core Chips
Balakrishnan, Anant
Naeemi, Azad
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (09) : 2831 - 2837
[6] HIGH-PERFORMANCE SIGNAL PROCESSING ON EMERGING MANY-CORE ARCHITECTURES USING CUDA
Ujaldon, Manuel
Catalyurek, Umit V.
ICME: 2009 IEEE INTERNATIONAL CONFERENCE ON MULTIMEDIA AND EXPO, VOLS 1-3, 2009, : 1821 - +
[7] A High-Performance Area-Efficient AES Cipher on a Many-Core Platform
Liu, Bin
Baas, Bevan M.
2011 CONFERENCE RECORD OF THE FORTY-FIFTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS (ASILOMAR), 2011, : 2058 - 2062
[8] Transparent many-core partitioning for high-performance big data I/O
Lee, Chan-Gyu
Cho, Joong-Yeon
Kim, Jooho
Jin, Hyun-Wook
CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2021, 33 (18):
[9] Hierarchical Dynamic Thermal Management Method for High-Performance Many-Core Microprocessors
Wang, Hai
Ma, Jian
Tan, Sheldon X. -D.
Zhang, Chi
Tang, He
Huang, Keheng
Zhang, Zhenghong
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2016, 22 (01)
[10] Silicon Photonic Memory Interconnect for Many-Core Architectures
Wen, Ke
Guan, Hang
Calhoun, David M.
Rumley, Sebastien
Bergman, Keren
Donofrio, David
Shall, John
2016 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC), 2016,

← 1 2 3 4 5 →