A nanophotonic interconnect for high-performance many-core computation

被引：41

作者：

Beausoleil, R. G. ^{[1
]}

Ahn, J. ^{[1
]}

Binkert, N. ^{[1
]}

Davis, A. ^{[1
]}

Fattal, D. ^{[1
]}

Fiorentino, M. ^{[1
]}

Jouppi, N. P. ^{[1
]}

McLaren, M. ^{[1
]}

Santori, C. M. ^{[1
]}

Schreiber, R. S. ^{[1
]}

Spillane, S. M. ^{[1
]}

Vantrease, D. ^{[1
]}

Xu, Q. ^{[1
]}

机构：

[1] HP Labs, Palo Alto, CA 94304 USA

来源：

16TH ANNUAL IEEE SYMPOSIUM ON HIGH-PERFORMANCE INTERCONNECTS, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/HOTI.2008.32

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Silicon nanophotonics holds the promise of revolutionizing computing by enabling parallel architectures that combine unprecedented performance and ease of use with affordable power consumption. Here we describe the results of a detailed multiyear design study of dense wavelength division multiplexing (DWDM) on-chip and off-chip interconnects and the device technologies that could improve computing performance by a factor of 20 above industry projections over the next decade.

引用

页码：182 / 189

页数：8

共 50 条

[11] A Compiler for High Performance Computing With Many-Core Accelerators
Nakasato, Naohito
Makino, Jun
2009 IEEE INTERNATIONAL CONFERENCE ON CLUSTER COMPUTING AND WORKSHOPS, 2009, : 629 - +
[12] SWIRL: High-performance many-core CPU code generation for deep neural networks
Venkat, Anand
Rusira, Tharindu
Barik, Raj
Hall, Mary
Truong, Leonard
INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS, 2019, 33 (06): : 1275 - 1289
[13] High-performance Multi/Many-core Network Processing Architectures with Shared and Private Queues
Falamarzi, Reza
Bahrambeigy, Bahram
Ahmadi, Mahmood
Rajabzade, Amir
2015 7TH CONFERENCE ON INFORMATION AND KNOWLEDGE TECHNOLOGY (IKT), 2015,
[14] A High-Performance Parallel CAVLC Encoder on a Fine-Grained Many-Core System
Xiao, Zhibin
Baas, Bevan
2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2008, : 248 - 254
[15] Adapting The Hyper-Ring Interconnect for Many-Core Processors
Sibai, Fadi N.
PROCEEDINGS OF THE 2008 INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS, 2008, : 649 - 654
[16] A Multilayer Nanophotonic Interconnection Network for On-Chip Many-core Communications
Zhang, Xiang
Louri, Ahmed
PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 156 - 161
[17] High-performance multi/many-core architectures with shared and private queues: Network processing approaches
Falamarzi, Reza
Bahrambeigy, Bahram
Ahmadi, Mahmood
Rajabzadeh, Amir
JOURNAL OF HIGH SPEED NETWORKS, 2018, 24 (02) : 89 - 106
[18] Dynamic Thread Mapping for High-Performance, Power-Efficient Heterogeneous Many-core Systems
Liu, Guangshuo
Park, Jinpyo
Marculescu, Diana
2013 IEEE 31ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2013, : 54 - 61
[19] High-performance optimizations on tiled many-core embedded systems: a matrix multiplication case study
Munir, Arslan
Koushanfar, Farinaz
Gordon-Ross, Ann
Ranka, Sanjay
JOURNAL OF SUPERCOMPUTING, 2013, 66 (01): : 431 - 487
[20] Near-Side Prefetch Throttling: Adaptive Prefetching for High-Performance Many-Core Processors
Heirman, Wim
Du Bois, Kristof
Vandriessche, Yves
Eyerman, Stijn
Hur, Ibrahim
27TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT 2018), 2018,

← 1 2 3 4 5 →