Molded Chip Scale Package for high pin count

被引：5
|
作者：
Baba, S [1 ]
Tomita, Y [1 ]
Matsuo, M [1 ]
Matsushima, H [1 ]
Ueda, N [1 ]
Nakagawa, O [1 ]
机构：
[1] MITSUBISHI ELECTR CORP,MFG TECHNOL DIV,IC ASSEMBLY ENGN DEPT,ITAMI,HYOGO 664,JAPAN
来源：
46TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1996 PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/ECTC.1996.550895
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
A unique Molded Chip Scale Package (CSP) associated 1024 pin counts has been developed. The design and process have been optimized in order to achieve high mount density, enhanced electrical characteristic and cost competitiveness. Also, the reliability testing was performed on thermal cycling and moisture induced crack resistivity. Finally, enhanced electrical and thermal characteristics were calculated.
引用
收藏
页码：1251 / 1257
页数：3
相关论文
共 50 条
  • [31] Molded Underfill (MUF) Encapsulation for Flip-Chip Package: A Numerical Investigation
    Azmi, M. A.
    Abdullah, K.
    Abdullah, M. Z.
    Ariff, Z. M.
    Saad, Abdullah Aziz
    Hamid, M. F.
    Ismail, M. A.
    PROCEEDING OF THE 3RD INTERNATIONAL CONFERENCE OF GLOBAL NETWORK FOR INNOVATIVE TECHNOLOGY 2016 (3RD IGNITE-2016): ADVANCED MATERIALS FOR INNOVATIVE TECHNOLOGIES, 2017, 1865
  • [32] A Novel Ultra-thin Package for Embedded High-pin-count LSI Supported by Cu Plate
    Mori, Kentaro
    Ohshima, Daisuke
    Sasaki, Hideki
    Fujimura, Yuki
    Kikuchi, Katsumi
    Nakashima, Yoshiki
    Funaya, Takuo
    Nishiyama, Tomohiro
    Murakami, Tomoo
    Yamamichi, Shintaro
    2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, : 1447 - +
  • [33] Thermal analysis of a Chip Scale Package technology
    Chambers, B
    Lee, TYT
    Blood, W
    48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS, 1998, : 1407 - 1412
  • [34] Chip scale package for image sensor device
    Chao, Yung-Ching
    Liu, John
    Lee, Yao-Jung
    Liu, De-Shin
    Wang, Jeff
    Chen, Ching-Yang
    Huang, Sam
    Lu, Alex
    ADVANCES IN ELECTRONIC PACKAGING 2005, PTS A-C, 2005, : 993 - 998
  • [35] Uncooled IRFPA with chip scale vacuum package
    Hata, Hisatoshi
    Nakaki, Yoshiyuki
    Inoue, Hiromoto
    Kosasayama, Yasuhiro
    Ohta, Yasuaki
    Fukumoto, Hiroshi
    Seto, Toshiki
    Kama, Keisuke
    Takeda, Munehisa
    Kimata, Masafumi
    INFRARED TECHNOLOGY AND APPLICATIONS XXXII, PTS 1AND 2, 2006, 6206
  • [36] Chip Scale Package and assembly joint reliability
    Ghaffarian, Reza
    National Electronic Packaging and Production Conference-Proceedings of the Technical Program (West and East), 1999, 1 : 497 - 505
  • [37] Silicone, chip scale package, and its reliability
    Lee, YJ
    FIFTH ANNUAL PAN PACIFIC MICROELECTRONICS SYMPOSIUM, PROCEEDINGS, 2000, : 345 - 353
  • [38] New stacked chip-scale package
    不详
    SOLID STATE TECHNOLOGY, 2001, 44 (03) : 42 - 42
  • [39] Development of a Low CTE Chip Scale Package
    Yamada, Tomoyuki
    Fukui, Masahiro
    Terada, Kenji
    Harazono, Masaaki
    Reynolds, Charles
    Audet, Jean
    Iruvanti, Sushumna
    Liu, Hsichang
    Moore, Scott
    Pan, Yi
    Zhang, Hongqing
    2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 944 - 948
  • [40] MicroSMD - A wafer level chip scale package
    Kelkar, N
    Mathew, R
    Takiar, H
    Nguyen, L
    IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2000, 23 (02): : 227 - 232
12345