GaN Power Transistors with Integrated Thermal Management

被引：5

作者：

Eddy, C. R., Jr. ^{[1
]}

Anderson, T. J. ^{[1
]}

Koehler, A. D. ^{[1
]}

Nepal, N. ^{[2
]}

Meyer, D. J. ^{[1
]}

Tadjer, M. J. ^{[2
]}

Baranyai, R. ^{[3
]}

Pomeroy, J. W. ^{[3
]}

Kuball, M. ^{[3
]}

Feygelson, T. I. ^{[1
]}

Pate, B. B. ^{[1
]}

Mastro, M. A. ^{[1
]}

Hite, J. K. ^{[1
]}

Ancona, M. G. ^{[1
]}

Kub, F. J. ^{[1
]}

Hobart, K. D. ^{[1
]}

机构：

[1] US Naval Res Lab, 4555 Overlook Ave SW, Washington, DC 20375 USA

[2] Amer Society Engn Educ, Washington, DC 200 USA

[3] Univ Bristol, HH Wills Phys Lab, Bristol BS8 1TL, Avon, England

来源：

GALLIUM NITRIDE AND SILICON CARBIDE POWER TECHNOLOGIES 3 | 2013年 / 58卷 / 04期

关键词：

EPITAXY;

D O I：

10.1149/05804.0279ecst

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

The concept for and design/fabrication of a GaN power transistor with integrated thermal management is presented. Key elements of the design, including those supporting enhancement-mode operation, high breakdown voltages and low on-resistance are described in detail. The importance of surface preparation and growth of high-kappa gate dielectrics using atomic layer deposition is summarized. Aspects of barrier design and surface passivation to promote low access resistance including lattice matched barriers and novel low-temperature AlN passivations are discussed. Finally, the integration of nanocrystalline diamond coatings on both the top-side and the back-side of the device for thermal management are described. Initial performance assessments of each of these components, as measured in the device operation, are presented and future efforts are highlighted.

引用

页码：279 / 286

页数：8

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