Low power SRAM design using charge sharing technique

被引：0

作者：

Ming, G ^{[1
]}

Jun, Y ^{[1
]}

Jun, X ^{[1
]}

机构：

[1] SE Univ, Natl ASIC Syst Engn Technol Res Ctr, Nanjing 210096, Peoples R China

来源：

2005 6th International Conference on ASIC Proceedings, Books 1 and 2 | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a low-power write scheme by adopting charge sharing technique. By reducing the bitlines voltage swing, the bitlines dynamic power is reduced. The memory cell's static noise margin (SNM) is discussed to proves it is a feasible scheme. Simulation results show compare to conventional SRAM, in write cycle this SRAM saves more than 20% dynamic power.

引用

页码：102 / 105

页数：4

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