Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches

被引:0
|
作者
Gruss, Daniel [1 ]
Spreitzer, Raphael [1 ]
Mangard, Stefan [1 ]
机构
[1] Graz Univ Technol, Graz, Austria
基金
欧盟地平线“2020”;
关键词
TIMING-ATTACK; IMPLEMENTATION;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Recent work on cache attacks has shown that CPU caches represent a powerful source of information leakage. However, existing attacks require manual identification of vulnerabilities, i.e., data accesses or instruction execution depending on secret information. In this paper, we present Cache Template Attacks. This generic attack technique allows us to profile and exploit cache based information leakage of any program automatically, without prior knowledge of specific software versions or even specific system information. Cache Template Attacks can be executed online on a remote system without any prior offline computations or measurements. Cache Template Attacks consist of two phases. In the profiling phase, we determine dependencies between the processing of secret information, e.g., specific key inputs or private keys of cryptographic primitives, and specific cache accesses. In the exploitation phase, we derive the secret values based on observed cache accesses. We illustrate the power of the presented approach in several attacks, but also in a useful application for developers. Among the presented attacks is the application of Cache Template Attacks to infer keystrokes and even more severe the identification of specific keys on Linux and Windows user interfaces. More specifically, for lower-case only passwords, we can reduce the entropy per character from log(2)(26) = 4.7 to 1.4 bits on Linux systems. Furthermore, we perform an automated attack on the T-table-based AES implementation of OpenSSL that is as efficient as state-of-the-art manual cache attacks.
引用
收藏
页码:897 / 912
页数:16
相关论文
共 50 条
  • [31] Managing Shared Last-Level Cache in a Heterogeneous Multicore Processor
    Mekkat, Vineeth
    Holey, Anup
    Yew, Pen-Chung
    Zhai, Antonia
    2013 22ND INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT), 2013, : 225 - 234
  • [32] Performance and Energy Assessment of Last-Level Cache Replacement Policies
    Peneau, Pierre-Yves
    Novo, David
    Bruguier, Florent
    Sassatelli, Gilles
    Gamatie, Abdoulaye
    PROCEEDINGS OF 2017 FIRST INTERNATIONAL CONFERENCE ON EMBEDDED & DISTRIBUTED SYSTEMS (EDIS 2017), 2017, : 149 - 154
  • [33] Filter cache: filtering useless cache blocks for a small but efficient shared last-level cache
    Han Jun Bae
    Lynn Choi
    The Journal of Supercomputing, 2020, 76 : 7521 - 7544
  • [34] Locality-Aware Data Replication in the Last-Level Cache
    Kurian, George
    Devadas, Srinivas
    Khan, Omer
    2014 20TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA-20), 2014, : 1 - 12
  • [35] Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches
    Oboril, Fabian
    Hameed, Fazal
    Bishnoi, Rajendra
    Ahari, Ali
    Naeimi, Helia
    Tahoori, Mehdi
    ISLPED '16: PROCEEDINGS OF THE 2016 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2016, : 236 - 241
  • [36] Filter cache: filtering useless cache blocks for a small but efficient shared last-level cache
    Bae, Han Jun
    Choi, Lynn
    JOURNAL OF SUPERCOMPUTING, 2020, 76 (10): : 7521 - 7544
  • [37] NoHammer: Preventing Row Hammer With Last-Level Cache Management
    Lee, Seunghak
    Kang, Ki-Dong
    Park, Gyeongseo
    Kim, Nam Sung
    Kim, Daehoon
    IEEE COMPUTER ARCHITECTURE LETTERS, 2023, 22 (02) : 157 - 160
  • [38] Access Pattern Characterization of Last-level Cache for Effective Replacement
    Anik, Shafayat Mowla
    Lee, Byeong Kil
    2023 INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE AND COMPUTATIONAL INTELLIGENCE, CSCI 2023, 2023, : 1113 - 1116
  • [39] Reducing Contention in Shared Last-Level Cache for Throughput Processors
    Kuo, Hsien-Kai
    Lai, Bo-Cheng Charles
    Jou, Jing-Yang
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2014, 20 (01) : 1 - 28
  • [40] Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design
    Chen, Yu-Ting
    Cong, Jason
    Huang, Hui
    Liu, Bin
    Liu, Chunyue
    Potkonjak, Miodrag
    Reinman, Glenn
    DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012), 2012, : 45 - 50