Reduction of Temperature Rise in 3D IC Routing

被引：0
|
作者：
Pandiaraj, K. [1 ]
Sivakumar, P. [1 ]
Geetharamani, N. [1 ]
机构：
[1] Kalasalingam Univ, ECE Dept, Virudunagar 626126, Tamil Nadu, India
来源：
2017 IEEE INTERNATIONAL CONFERENCE ON ELECTRICAL, INSTRUMENTATION AND COMMUNICATION ENGINEERING (ICEICE) | 2017年
关键词：
3D IC; Thermal Through Silicon Via (TTSV); Thermal aware; IBM-route benchmark; GLOBAL ROUTER; 3-D ICS; MINIMIZATION;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
In Three Dimensional Integration Circuit (3D IC) challenges involved in removing heat from the intervening layers. Here, the thermal analysis of TTSVs (Thermal Through Silicon Vias) at the heat sink of the circuit and also the optimizations of corresponding heat sinks has been carried out using Genetic algorithm (GA) with IBM-route benchmark circuits as a inputs. Compared to the previous experimental results, the thermal aware between the routing layers in 3D IC has been reduced to a certain extent using this algorithmic approach. Our approach is achieves 7%.
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页数：5
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