A describing method of latency tolerant hardware for a pure ANSI-C/C plus plus based high-level synthesis technology

The image processing is important for the robotics and its hardware implementation is required in order to realize a small and low-power device with the appropriate performance where the high performance computer cannot be used due to the cost, size and power limitation. To reduce the burden of such hardware development, the high-level synthesis (HLS) technologies that automatically convert the algorithmic description to hardware have been proposed and developed. The combination of the memory latency hiding and data process pipelining is very important to extract the hardware performance maximally. However, nobody shows clearly how to describe the hardware behavior to generate such hardware. This paper shows a generic describing method for HLS technology based on ANSI-C/ C++ that can realize the combination of the memory latency hiding and data process pipelining. The experimental results show that our method can be applied easily to the intuitive C program. The logic simulation and an FPGA implementation reveal the effects to the performance improvement and the hardware increase induced by our method.