共 50 条
- [1] An interactive design environment for C-based high-level synthesis EMBEDDED SYSTEM DESIGN: TOPICS, TECHNIQUES AND TRENDS, 2007, 231 : 135 - +
- [3] C-based High-level Synthesis system, "Cyber" - Design experience NEC RESEARCH & DEVELOPMENT, 2000, 41 (03): : 264 - 268
- [4] Loop Coarsening in C-based High-Level Synthesis PROCEEDINGS OF THE ASAP2015 2015 IEEE 26TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2015, : 166 - 173
- [5] Enriching C-Based High-Level Synthesis with Parallel Pattern Templates 2016 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), 2016, : 177 - 180
- [6] Detecting Kernels Suitable for C-based High-Level Hardware Synthesis 2016 INT IEEE CONFERENCES ON UBIQUITOUS INTELLIGENCE & COMPUTING, ADVANCED & TRUSTED COMPUTING, SCALABLE COMPUTING AND COMMUNICATIONS, CLOUD AND BIG DATA COMPUTING, INTERNET OF PEOPLE, AND SMART WORLD CONGRESS (UIC/ATC/SCALCOM/CBDCOM/IOP/SMARTWORLD), 2016, : 1157 - 1164
- [7] SpExSim: assessing kernel suitability for C-based high-level hardware synthesis The Journal of Supercomputing, 2019, 75 : 4062 - 4077
- [8] CHStone: A benchmark program suite for practical C-based high-level synthesis PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 1192 - +
- [9] SpExSim: assessing kernel suitability for C-based high-level hardware synthesis JOURNAL OF SUPERCOMPUTING, 2019, 75 (08): : 4062 - 4077