On the yield of VLSI processors with on-chip CPU cache

Yield enhancement through the acceptance of partially good chips is a well-known technique [1], [2], [3]. In this paper, we derive a yield model for single chip VLSI processors with partially good on-chip cache. Also, we investigate how the yield enhancement of VLSI processors with on-chip CPU cache relates with the number of acceptable faulty cache blocks, the percentage of the cache area with respect to the whole chip area, and various manufacturing process parameters as defect densities and the fault clustering parameter. One of the main conclusions is that the maximum effective yield is achieved by accepting as good, caches with a very small number of faulty cache blocks. One of the main conclusions is that the maximum effective yield is achieved by accepting as good, processor chips containing caches with a very small number of faulty cache blocks.