Scalable Rasterizer Architecture for 3D Graphics System

In this paper, a cost-effective and scalable edge-equation-based rasterizer algorithm and architecture for OpenGL ES Applications is proposed. The architecture consists of three main components which includes the Setup PE with four-stage operand scheduler, equation coefficient memory, and the tile generation stage. The Setup PE contains four float-point multipliers, three float-point adders, and four special operand units. The equation coefficient memory store the compact results of design consideration from Geometry engine to Pixel rendering engine. The tile generation stage contains four float-point multipliers, eight float-point adders, and four special operand units. Based on the optimize perspective correction algorithm, pipelined architecture is derived to shorten the data path. The proposed scalable architecture which processes the tile traversal for each primitive in 9 cycles; we had implemented the full function of Rasterizer suitable for OpenGL ES 2.0, including the anti-aliasing function and Hierarchical-Z test. The gate counts is 230.45k plus 14.43kB SRAM ( SETUP 512B + rf_2p_40x96 + TGS internal SRAM 13.44kB) using the 90nm 1P9M process @ 200MHZ; the scalable unit resolution is 720P@60HZ and the throughput reaches 3M Triangles/Sec.