Thermal-aware detour routing in 3D NoCs

Three-dimensional Network-on-Chips (3D NoCs) is a popular design choice due to its low packet latency, low network power consumption and high packing density. However, 3D NoCs suffer from high temperature issues. The 3D stacking of Si-layers elongates heat transfer path from different Si-layers to the heat sink resulting in increase in peak temperature of the chip. Since routers of NoCs have high power densities, a higher router activity may result in signification increase in temperature of the chip. Therefore, a judicious selection of the routing path is necessary to reduce the chip temperature. As the routers placed at the lower Si-layers have higher thermal conductance to the heat sink, a routing path consisting of more number of routers in the lower Si-layers may improve the temperature profile of the chip. In this paper, we have proposed two different thermal-aware routing approaches, which use downward detoured routing for some optimally selected communication paths to reduce the chip temperature. The first technique is a thermal-aware application-specific Mixed Integer Linear Programming based method (named TMD), while the second one is an application-agnostic heuristic approach (named TSD). To predict the effect of detour decisions on the temperature profile of the chip, TMD technique has applied two different thermal models with a constraint on the average packet delay (APD) of the network. Experimental results show that a significant temperature reduction (up to 22 degrees) can be achieved within minimal performance loss (10% increase in APD) using either of the proposed techniques, compared to the minimal path routing algorithms - XYZ, ZXY and EDGE and the greedy detour approaches - All Detour and Random Detour. (C) 2020 Elsevier Inc. All rights reserved.