The design of an asynchronous carry-lookahead adder based on data characteristics

被引：0

作者：

Liu, YJ ^{[1
]}

Furber, S ^{[1
]}

机构：

[1] Univ Manchester, Sch Comp Sci, APT Grp, Manchester M13 9PL, Lancs, England

来源：

INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2005年 / 3728卷

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Addition is the most important operation in data processing and its speed has a significant impact on the overall performance of digital circuits. Therefore, many techniques have been proposed for fast adder design. An asynchronous ripple-carry adder is claimed to use a simple circuit implementation to gain a fast average performance as long as the worst cases input patterns rarely happen. However, based on the input vectors from a number of benchmarks, we observe that the worst cases are not exceptional but commonly exist. A simple carry-lookahead scheme is proposed in the paper to speed up the worst-case delay of a ripple-carry adder. The experiment result shows the proposed adder is about 25% faster than an asynchronous ripple-carry adder with only small area and power overheads.

引用

页码：647 / 656

页数：10

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