The study of silicon die stress in stacked die packages

被引：0
|
作者：
Yamada, Eiichi [1 ]
Abe, Kenji [1 ]
Suzuki, Yutaka [1 ]
Amagai, Masazumi [1 ]
机构：
[1] Texas Instruments Japan Ltd, Tsukuba, Ibaraki, Japan
来源：
EMAP 2005: International Symposium on Electronics Materials and Packaging | 2005年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The purpose of the present study is to understand the overhang size effect of stacked die package on a chip. The deflection and stress in the chip as during wire bonding are evaluated using finite element model. It is considered that stresses in the part of top die over the spacer edge, and effect of the thickness on the chip is discussed. Also, this study provides stresses of the structure around a bond pad during bonding process. The stress of a top die is investigated for two types of spacer materials, silicon and resin spacer, respectively.
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页码：74 / 77
页数：4
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