Reliability driven module generation for analog layouts

被引：0

作者：

Wolf, M ^{[1
]}

Kleine, U ^{[1
]}

机构：

[1] Otto Von Guericke Univ, Inst Measurement Technol & Elect IPE, D-39016 Magdeburg, Germany

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 6: CIRCUITS ANALYSIS, DESIGN METHODS, AND APPLICATIONS | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper new features of a module generator environment [11] will be presented for reliability improvements in analog circuit layouts. The reliability of analog layouts is improved by an automatic check of electrical constraints like electromigration and voltage drop due to interconnection resistances after the modules have been generated. If a check failed constraints are automatically added and the layout is automatically rebuilt. The new features will be demonstrated with several layout examples.

引用

页码：412 / 415

页数：4

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