Fault-Tolerant Mechanisms for Relocation-Aware Dynamic On-Chip Communication on FPGAs

Fault tolerance has become more important in modern chips. This is because of the increasing use of smaller process nodes. Though there has been a tremendous increase in the integrating density of transistors, the miniaturized size has made them more vulnerable to ageing-and radiation-induced hard errors. In this paper, we present mechanisms for tackling soft and hard errors in CERANoC, a Clock-Enabled Relocation-Aware Network-on-Chip. It has been developed as a communication network that facilitates the online relocation of circuits in response to hard errors. This highlights why it is important that the network itself is resilient to errors.