MASkIt: Soft Error Rate Estimation for Combinational Circuits

被引:0
|
作者
Anglada, Marti [1 ]
Canal, Ramon [1 ]
Aragon, Juan L. [2 ]
Gonzalez, Antonio [1 ]
机构
[1] Univ Politecn Cataluna, E-08028 Barcelona, Spain
[2] Univ Murcia, E-30001 Murcia, Spain
来源
PROCEEDINGS OF THE 34TH IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD) | 2016年
关键词
PROPAGATION;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Integrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft error rate (SER) estimation has become an important and very challenging goal. In this work, a novel approach for SER estimation of combinational circuits is presented. The proposed framework is divided in two stages. First, signal probabilities are computed via a hybrid approach combining heuristics and selective simulation of reconvergent subnets. In the second stage, signal probabilities are used to compute the vulnerability of all the gates in a combinational block using a backward-traversing algorithm that takes into account logical, electrical and timing masking factors. Experimental results show that our signal probability estimation approach, in comparison with similar techniques in the literature, reduces innacuracy by 96% while adding minimal execution time overhead. In addition, results indicate that our framework is two orders of magnitude faster than traditional Monte Carlo-based fault injection with minor loss in accuracy in both signal probability and SER estimation (average error of 5%).
引用
收藏
页码:614 / 621
页数:8
相关论文
共 50 条
  • [21] Enhanced architectures for soft error detection and correction in combinational and sequential circuits
    Krstic, Milos
    Weidling, Stefan
    Petrovic, Vladimir
    Sogomonyan, Egor S.
    MICROELECTRONICS RELIABILITY, 2016, 56 : 212 - 220
  • [22] An efficient static algorithm for computing the soft error rates of combinational circuits
    Rao, Rajeev R.
    Chopra, Kaviraj
    Blaauw, David
    Sylvester, Dennis
    2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS, 2006, : 162 - +
  • [23] Impact of Technology Scaling on the Combinational Logic Soft Error Rate
    Mahatme, N. N.
    Gaspard, N. J.
    Assis, T.
    Jagannathan, S.
    Chatterjee, I.
    Loveless, T. D.
    Bhuva, B. L.
    Massengill, L. W.
    Wen, S. J.
    Wong, R.
    2014 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2014,
  • [24] Soft error rate analysis for sequential circuits
    Miskov-Zivanov, Natasa
    Marculescu, Diana
    2007 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3, 2007, : 1436 - 1441
  • [25] Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits
    El-Maleh, Aiman H.
    Daud, Khaled A. K.
    IEEE TRANSACTIONS ON RELIABILITY, 2015, 64 (03) : 935 - 948
  • [26] Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits
    Li, Linzhe
    Xiao, Liyi
    Liu, He
    Mao, Zhigang
    IEEE ACCESS, 2022, 10 : 64161 - 64171
  • [27] Analysis of the Impact of Electrical and Timing Masking on Soft Error Rate Estimation in VLSI Circuits
    Tsoumanis, Pelopidas
    Paliaroutis, Georgios Ioannis
    Evmorfopoulos, Nestor
    Stamoulis, George
    TECHNOLOGIES, 2022, 10 (01)
  • [28] Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs)
    Fazeli, Mahdi
    Ahmadian, Seyed Nematollah
    Miremadi, Seyed Ghassem
    Asadi, Hossein
    Tahoori, Mehdi B.
    2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 70 - 75
  • [29] Modeling the effect of technology trends on the soft error rate of combinational logic
    Shivakumar, P
    Kistler, M
    Keckler, SW
    Burger, D
    Alvisi, L
    INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS, PROCEEDINGS, 2002, : 389 - 398
  • [30] Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic
    Georgakidis, Christos
    Paliaroutis, Georgios Ioannis
    Sketopoulos, Nikolaos
    Tsoumanis, Pelopidas
    Sotiriou, Christos
    Evmorfopoulos, Nestor
    Stamoulis, Georgios
    PROCEEDINGS OF THE TWENTYFIRST INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2020), 2020, : 231 - 236