Novel CuCMP Slurry Evaluation for 45/40nm BEOL Low-k Technology and Beyond

被引:0
|
作者
Zhao, Feng [1 ]
Liu, Hongtao [1 ]
Hu, Tony [1 ]
Chen, Feng [1 ]
Liu, Kent [1 ]
Deng, Wufeng [1 ]
Cao, Junzhu [1 ]
Zhou, Sky [1 ]
Zhang, Jason [1 ]
Zhou, Erico [1 ]
Song, Kerry [1 ]
Zhao, Jun [1 ]
Bao, Ethan [1 ]
Chen, Larry [1 ]
机构
[1] Semicond Mfg Int Corp, Pudong New Area, Shanghai 201203, Peoples R China
关键词
D O I
10.1149/1.3694365
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
Novel CuCMP slurry was evaluated under different polishing conditions and its impact on topography, thickness and in line test performance was investigated. Generally, topography, such as dishing and erosion, results from over-polishing after Cu polishing step and it can be modified and reduced by fine tuning process parameters. Firstly, different Cu polishing condition has been attempted to produce different topography for barrier polishing to compensate in order to cater for different integration scheme with different oxide material. Secondly, topography can be modified by barrier polishing condition due to high selectivity slurry is used during barrier polishing. Longer polishing time can cause Cu protruded in narrow dense arrays. Electrical data shows Cu polishing overpolishing time has impact on Rs, and longer overpolishing results in higher Rs, as well as high head/platen rotation speed.
引用
收藏
页码:531 / 536
页数:6
相关论文
共 50 条
  • [21] Comprehensive reliability evaluation of a 90 mn CMOS technology with Cu/PECVD low-K BEOL
    Edelstein, D
    Rathore, H
    Davis, C
    Clevenger, L
    Cowley, A
    Nogami, T
    Agarwala, B
    Arai, S
    Carbone, A
    Chanda, K
    Chen, F
    Cohen, S
    Cote, W
    Cullinan, M
    Dalton, T
    Das, S
    Davis, P
    Demarest, J
    Dunn, D
    Dziobkowski, C
    Filippi, R
    Fitzsimmons, J
    Flaitz, P
    Gates, S
    Gill, J
    Grill, A
    Hawken, D
    Ida, K
    Klaus, D
    Klymko, N
    Lane, M
    Lane, S
    Lee, J
    Landers, W
    Li, WK
    Lin, YH
    Liniger, E
    Liu, XH
    Madan, A
    Malhotra, S
    Martin, J
    Molis, S
    Muzzy, C
    Nguyen, D
    Nguyen, S
    Ono, M
    Parks, C
    Questad, D
    Restaino, D
    Sakamoto, A
    2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS, 2004, : 316 - 319
  • [22] Low temperature dry cleaning technology using formic acid in Cu/low-k multilevel interconnects for 45 nm node and beyond
    Nakahira, J
    Ishikawa, K
    Nishikawa, N
    Hayashi, M
    Akbar, AA
    Nakata, Y
    Mizushima, Y
    Kudo, H
    Kurahashi, T
    Mishima, Y
    Takigawa, Y
    Nakaishi, M
    Ohba, T
    Watanabe, K
    Advanced Metallization Conference 2005 (AMC 2005), 2006, : 569 - 574
  • [23] Integration of a poisoning-free dual damascene CDO film stack for 90 nm & beyond low-k BEOL
    Liu, WP
    Tan, JB
    Lu, W
    Pal, S
    Siew, YK
    Cong, H
    Zhang, BC
    Wang, XB
    Zhang, F
    Hsia, LC
    2005 IEEE VLSI-TSA International Symposium on VLSI Technology (VLSI-TSA-TECH), Proceedings of Technical Papers, 2005, : 70 - 71
  • [24] Robust BEOL process integration with ultra low-k (k=2.0) dielectric and self-formed MnOx barrier technology for 32 nm-node and beyond
    Watanabe, T.
    Hayashi, Y.
    Tomizawa, H.
    Usui, T.
    Gawase, A.
    Shimada, M.
    Watanabe, K.
    Shibata, H.
    PROCEEDINGS OF THE IEEE 2008 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2008, : 208 - +
  • [25] A high performance 0.13 μm copper BEOL technology with low-k dielectric
    Goldblatt, RD
    Agarwala, B
    Anand, MB
    Barth, EP
    Biery, GA
    Chen, ZG
    Cohen, S
    Connolly, JB
    Cowley, A
    Dalton, T
    Das, SK
    Davis, CR
    Deutsch, A
    De Wan, C
    Edelstein, DC
    Emmi, PA
    Faltermeier, CG
    Fitzsimmons, JA
    Hedrick, J
    Heidenreich, JE
    Hu, CK
    Hummel, JP
    Jones, P
    Kaltalioglu, E
    Kastenmeier, BE
    Krishnan, M
    Landers, WF
    Liniger, E
    Liu, J
    Lustig, NE
    Malhotra, S
    Manger, DK
    McGahay, V
    Mih, R
    Nye, HA
    Purushothaman, S
    Rathore, HA
    Seo, SC
    Shaw, TM
    Simon, AH
    Spooner, TA
    Stetter, M
    Wachnik, RA
    Ryan, JG
    PROCEEDINGS OF THE IEEE 2000 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2000, : 261 - 263
  • [26] Robust Low-k film (k=2.1-2.5) for 90/65 nm BEOL technology using BiLayer film schemes
    Chang, HL
    Lu, YC
    Li, LP
    Chen, BT
    Lin, KC
    Jeng, SM
    Jang, SM
    Liang, MS
    PROCEEDINGS OF THE IEEE 2004 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2004, : 181 - 183
  • [27] BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65 nm groundrules
    Fukasawa, M
    Lane, S
    Angyal, M
    Chanda, K
    Chen, F
    Christiansen, C
    Fitzsimmons, J
    Gill, J
    Ida, K
    Inoue, K
    Kumar, K
    Li, B
    McLaughlin, P
    Melville, I
    Minami, M
    Nguyen, S
    Penny, C
    Sakamoto, A
    Shimooka, Y
    Ono, M
    McHerron, D
    Nogami, T
    Ivers, T
    PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2005, : 9 - 11
  • [28] 32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k=2.3
    Hamioud, K.
    Arnal, V.
    Farcy, A.
    Jousseaume, V.
    Zenasni, A.
    Icard, B.
    Pradelles, J.
    Manakli, S.
    Brun, Ph.
    Imbert, G.
    Jayet, C.
    Assous, M.
    Maitrejean, S.
    Galpin, D.
    Monget, C.
    Guillan, J.
    Chhun, S.
    Richard, E.
    Barbier, D.
    Haond, M.
    MICROELECTRONIC ENGINEERING, 2010, 87 (03) : 316 - 320
  • [29] Challenge of low-k materials for 130, 90, 65 nm node interconnect technology and beyond
    Miyajima, H
    Watanabe, K
    Fujita, K
    Ito, S
    Tabuchi, K
    Shimayama, T
    Akiyama, K
    Hachiya, T
    Higashi, K
    Nakamura, N
    Kajita, A
    Matsunaga, N
    Enomoto, Y
    Kanamura, R
    Inohara, M
    Honda, K
    Kamijo, H
    Nakata, R
    Yano, H
    Hayasaka, N
    Hasegawa, T
    Kadomura, S
    Shibata, H
    Yoda, T
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 329 - 332
  • [30] BEOL Layout Optimization to Improve RF Performance of 40nm Node Technology for High-Frequency Applications
    Das, Avishek
    Lin, Hsin-Cheng
    Liu, C. W.
    2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA, 2024,