BEOL Layout Optimization to Improve RF Performance of 40nm Node Technology for High-Frequency Applications

被引：0
|
作者：
Das, Avishek [1 ]
Lin, Hsin-Cheng [2 ]
Liu, C. W. [1 ,2 ]
机构：
[1] Natl Taiwan Univ, Grad Sch Adv Technol, Taipei, Taiwan
[2] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei, Taiwan
来源：
2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA | 2024年
关键词：
D O I：
10.1109/VLSITSA60681.2024.10546360
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
RF performance considering different transistor array layouts is studied and optimized by validated TCAD simulation. A Hybrid-Contact layout scheme is proposed to improve RF performance by reducing the gate parasitic capacitance and resistance from the interconnects. Optimizing the gate contacts and source-to-drain interconnection lines, the proposed layout improves maximum oscillation frequency up to 699 GHz without the cut-off frequency degradation as compared to the original Double Side Gate Contact layout.
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