A high-speed low-power 0.3 mu m CMOS gate array with variable threshold voltage (VT) scheme

被引：19

作者：

Kuroda, T ^{[1
]}

Fujita, T ^{[1
]}

Nagamatu, T ^{[1
]}

Yoshioka, S ^{[1
]}

Sei, T ^{[1
]}

Matsuo, K ^{[1
]}

Hamura, Y ^{[1
]}

Mori, T ^{[1
]}

Murota, M ^{[1
]}

Kakumu, M ^{[1
]}

Sakurai, T ^{[1
]}

机构：

[1] TOSHIBA CO LTD,SEMICOND DEVICE ENGN LAB,KAWASAKI,KANAGAWA 210,JAPAN

来源：

PROCEEDINGS OF THE IEEE 1996 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1996年

关键词：

D O I：

10.1109/CICC.1996.510510

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：53 / 56

页数：4

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