A Correlation Study of MOL Electrical Test Method with its Physical Analysis

被引：0

作者：

Cahyadi, T. ^{[1
]}

Chen, F. ^{[2
]}

Jiang, H. ^{[1
]}

Mittl, S. ^{[2
]}

Chua, E. C. ^{[1
]}

机构：

[1] GLOBALFOUNDRIES US Inc, 400 Stone Break Rd Ext, Malta, NY 12020 USA

[2] IBM Microelect, Essex Jct, VT 05452 USA

来源：

PROCEEDINGS OF THE 2013 20TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2013) | 2013年

关键词：

Middle-of-Line; MOL; VRDB; PC-to-CA reliability; PC-to-CA space; local variation; global variation; fatal-area ratio; PC-to-CA overlay;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A correlation study of middle-of-line (MOL) electrical test method with its inline polysilicon gate (PC) and the diffusion contacts (CA) photolithography overlay data is presented in this paper for wafers fabricated by gate first CMOS process at 32nm. The physical analysis by scanning electron microscopy (SEM) further confirmed the accuracy of the electrical test method in explaining the physical values of global shift and local shift. Therefore, this electrical PC-to-CA testing methodology can be adopted cost effectively for an accurate MOL reliability assessment and process diagnostics in a timely and comprehensive manner.

引用

页码：217 / 220

页数：4

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