Performance evaluation of the fixed sequential prefetching on a bus-based multiprocessor: Preliminary results

被引：0
|
作者：
Ordonez, EDM [1 ]
Kofuji, ST [1 ]
机构：
[1] UNIV SAO PAULO,INTEGRATED SYST LAB,DEPT ELECTR ENGN,BR-05508900 SAO PAULO,BRAZIL
来源：
SECOND INTERNATIONAL SYMPOSIUM ON PARALLEL ARCHITECTURES, ALGORITHMS, AND NETWORKS (I-SPAN '96), PROCEEDINGS | 1996年
关键词：
prefetching techniques; fixed sequential prefetching; extensions OBL policy; shared-memory systems; petri nets;
D O I：
10.1109/ISPAN.1996.509030
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：487 / 493
页数：7
相关论文
共 50 条
  • [1] Performance evaluation of a bus-based multistage multiprocessor architecture
    Veglis, A
    Pombortsis, A
    Papaefstathiou, E
    JOURNAL OF SYSTEMS ARCHITECTURE, 2000, 46 (01) : 39 - 47
  • [2] Performance evaluation of a cluster-based multiprocessor built from ATM switches and bus-based multiprocessor servers
    Karlsson, Magnus
    Stenstrom, Per
    Doktorsavhandlingar vid Chalmers Tekniska Hogskola, 1999, (1552): : 4 - 13
  • [3] Performance evaluation of a cluster-based multiprocessor built from ATM switches and bus-based multiprocessor servers
    Karlsson, M
    Stenstrom, P
    SECOND INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, 1996, : 4 - 13
  • [4] Adaptive routing for a bus-based multiprocessor
    Fazio, VJ
    ICA(3)PP 97 - 1997 3RD INTERNATIONAL CONFERENCE ON ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, 1997, : 37 - 50
  • [5] Effective cache prefetching on bus-based multiprocessors
    ACM Trans Comput Syst, 1 (57):
  • [6] EFFECTIVE CACHE PREFETCHING ON BUS-BASED MULTIPROCESSORS
    TULLSEN, DM
    EGGERS, SJ
    ACM TRANSACTIONS ON COMPUTER SYSTEMS, 1995, 13 (01): : 57 - 88
  • [7] An analysis of an improved bus-based multiprocessor architecture
    Ricks, KG
    Wells, BE
    INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-IV, PROCEEDINGS, 1998, : 1447 - 1454
  • [8] Global bus design of a bus-based COMA multiprocessor DICE
    Lee, GH
    Quattlebaum, B
    Cho, SY
    Kinney, L
    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1996, : 231 - 240
  • [9] On timing constraints of snooping in a bus-based COMA multiprocessor
    Cho, SY
    Kong, JK
    Lee, GH
    MICROPROCESSORS AND MICROSYSTEMS, 1998, 21 (05) : 313 - 318
  • [10] Design of a bus-based shared-memory multiprocessor DICE
    Lee, GH
    Quattlebaum, BW
    Cho, SY
    Kinney, LL
    MICROPROCESSORS AND MICROSYSTEMS, 1999, 22 (07) : 403 - 411
12345