A digital BIST for operational amplifiers embedded in mixed-signal circuits

被引：14
|
作者：
Rayane, I [1 ]
Velasco-Medina, J [1 ]
Nicolaidis, M [1 ]
机构：
[1] Inst Natl Polytech Grenoble, TIMA, F-38031 Grenoble, France
来源：
17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1999年
关键词：
D O I：
10.1109/VTEST.1999.766680
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new digital BIST structure is proposed in this paper. During test mode, the Op Antp under test is placed in a voltage follower configuration in order to detect its slew-rate deviation, or in a comparator configuration in order to detect its signal propagation delay deviation. The test stimuli and the BIST control signals are simply derived from the test control signal TST using delay elements and logical gates. The test response is analyzed by using a pure digital circuitry. Simulation results show the effectiveness of the proposed technique with a low area overhead.
引用
收藏
页码：304 / 310
页数：3
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