An Efficient Error Estimation Technique for Pruning Approximate Data-Flow Graphs in Design Space Exploration

In this paper, we present an error estimation and propagation technique which targets high-level design abstraction through considering data-flow graph (DFG) representation of approximate circuits. The proposed technique is utilized for pruning different combinations of exact versus approximate realizations of various operations in the DFG for a design space exploration (DSE) framework The technique relies on the output error estimation of the arithmetic modules of a high-level library by dividing the input range to intervals and then considering different combinations of these intervals (cluster-based estimation of output error). Additionally, the estimation considers the error of the operands. The error for each combination is stored in a look up table (LUT). The efficacy of the proposed method is assessed for two image processing applications. Simulation results show that the framework can efficiently generate the Pareto frontier in the trade-off space of accuracy versus energy efficiency for the two applications.