A 65nm low power CMOS platform with 0.495μm2 SRAM for digital processing and mobile applications

被引：0

作者：

Utsumi, K ^{[1
]}

Morifuji, E ^{[1
]}

Kanda, M ^{[1
]}

Aota, S ^{[1
]}

Yoshida, T ^{[1
]}

Honda, K ^{[1
]}

Matsubara, Y ^{[1
]}

Yamada, S ^{[1
]}

Matsuoka, F ^{[1
]}

机构：

[1] Semicond Co, Toshiba Corp, Syst LSI Div, Yokohama, Kanagawa 2358582, Japan

来源：

2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a 65nm CMOS platform featuring low power transistors and high density SRAM(CMOS5L) is reported. It offers wide range of Vth lineup and very low gate leakage as 0.06A/cm(2) by optimization of halo implantation and gate oxidation process. Pulse nitridation is applied to suppress Vth variations. Obtained characteristics of MOSFET places top class among devices reported. High density SRAM for CMOS5L with the cell size of 0.495 mu m(2) is developed. We demonstrate highly stable operation by 7Mb CMOS5L SRAM array. This SRAM has low power property less than 100 mu W.

引用

页码：216 / 217

页数：2

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