Field Programmable Gate Arrays - Detecting Cosmic Rays

被引:0
|
作者
Dasgupta, S. [1 ]
Cussans, D. [1 ]
机构
[1] Univ Bristol, HH Wills Phys Lab, Bristol BS8 1TL, Avon, England
来源
关键词
VLSI circuits; Trigger concepts and systems (hardware and software); Front-end electronics for detector readout; Digital electronic circuits;
D O I
10.1088/1748-0221/10/07/C07006
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
Field Programmable Gate Arrays (FPGAs) are finding extensive application in instrumentation for particle physics experiments. A table-top framework is developed using FPGA-based hardware to detect the coincidence of signals produced by cosmic rays in multiple detectors. The rates of the detector signals and coincidence output are also measured. The logic is programmed inside an FPGA mounted on a Xilinx evaluation board. Control and data readout are carried out using IPbus, a gigabit Ethernet-based protocol developed as part of upgrading the Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC). The framework is appropriate for introducing students to FPGA-based instrumentation and providing them with a practical experience of working with such hardware.
引用
收藏
页数:4
相关论文
共 50 条
  • [41] DBPM signal processing with field programmable gate arrays
    LAI Longwei~(1
    [J]. Nuclear Science and Techniques, 2011, 22 (03) : 129 - 133
  • [42] Are Field-Programmable Gate Arrays Ready for the Mainstream?
    Stitt, Greg
    [J]. IEEE MICRO, 2011, 31 (06) : 58 - 63
  • [43] Implementation of ANN Training Module on Field Programmable Gate Arrays
    Sarvan, Cagla
    Gunduzalp, Mustafa
    [J]. 2019 INNOVATIONS IN INTELLIGENT SYSTEMS AND APPLICATIONS CONFERENCE (ASYU), 2019, : 258 - 263
  • [44] A simulation tool for dynamically reconfigurable field programmable gate arrays
    Lysaght, P
    Stockwood, J
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1996, 4 (03) : 381 - 390
  • [45] Design of Sobel Operator Using Field Programmable Gate Arrays
    Alghurair, Dina
    Al-Rawi, Sefwan S.
    [J]. 2013 INTERNATIONAL CONFERENCE ON TECHNOLOGICAL ADVANCES IN ELECTRICAL, ELECTRONICS AND COMPUTER ENGINEERING (TAEECE), 2013, : 589 - 594
  • [46] FIELD PROGRAMMABLE GATE ARRAYS CUT COSTS, UP PERFORMANCE
    GUTIERREZ, K
    [J]. I&CS-CONTROL TECHNOLOGY FOR ENGINEERS AND ENGINEERING MANAGEMENT, 1990, 63 (05): : 67 - 70
  • [47] Power Aware Architecture Exploration for Field Programmable Gate Arrays
    Goeders, Jeffrey B.
    Wilton, Steven J. E.
    [J]. JOURNAL OF LOW POWER ELECTRONICS, 2014, 10 (03) : 297 - 312
  • [48] Depth optimal incremental mapping for field programmable gate arrays
    Cong, J
    Huang, H
    [J]. 37TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2000, 2000, : 290 - 293
  • [49] Testable clock routing architecture for field programmable gate arrays
    Kumar, LK
    Mupid, AJ
    Ramani, AS
    Kamakoti, V
    [J]. FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2003, 2778 : 1044 - 1047
  • [50] Multivariable controller implementation using field programmable gate arrays
    Rao, VS
    Pottinger, H
    Kelly, JS
    Yuan, LF
    Varadharajan, S
    [J]. SMART STRUCTURES AND MATERIALS 1998: SMART ELECTRONICS AND MEMS, 1998, 3328 : 297 - 300