A simplified distribution parasitic capacitance model for on-chip spiral inductors

被引：0
|
作者：
Masuda, T [1 ]
Kodama, A
Nakamura, T
Shiramizu, N
Wada, S
Hashimoto, T
Washio, K
机构：
[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo 1858601, Japan
[2] Renesas Northern Japan Semicond, Tokyo, Japan
[3] Hitachi Ltd, Micro Device Div, Tokyo, Japan
来源：
2006 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS, DIGEST OF PAPERS | 2006年
关键词：
spiral inductor; equivalent circuit model; parasitic capacitance; silicon substrate;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A modeling methodology for determining simply distributed parasitic capacitances used in a lumped equivalent circuit of silicon monolithic spiral inductors is proposed. To calculate the capacitances for the obtained model, the degeneration factors for the total amount of distributed parasitic-capacitances are introduced. A Q-factor modeling-error of less than 9.4% was obtained by comparing the measured and modeled characteristics in the microwave region.
引用
收藏
页码：111 / +
页数：2
相关论文
共 50 条
  • [1] Analysis of on-chip spiral inductors using the distributed capacitance model
    Wu, CH
    Tang, CC
    Liu, SI
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (06) : 1040 - 1044
  • [2] Analysis of on-chip spiral inductors using the distributed capacitance model
    Wi, CH
    Tang, CC
    Liu, SI
    [J]. 2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS, 2002, : 259 - 262
  • [3] Scalable distributed-capacitance model for silicon on-chip spiral inductors
    Huang, Fengyi
    Lu, Jingxue
    Jiang, Nan
    [J]. MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2006, 48 (07) : 1423 - 1427
  • [4] Compact model for on-chip spiral inductors
    Wang, JN
    Rowland, J
    Zhu, XY
    Hutchens, C
    Zhang, YM
    [J]. 2004 IEEE REGION 5 CONFERENCE: ANNUAL TECHNICAL AND LEADERSHIP WORKSHOP, 2004, : 99 - 101
  • [5] A comprehensive model for on-chip spiral inductors
    Hosseinieh, BK
    Masoumi, N
    [J]. Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, 2005, : 127 - 131
  • [6] Modeling of on-chip spiral inductors
    Hashemi, S
    Safarian, Z
    Masoumi, N
    [J]. 17th ICM 2005: 2005 International Conference on Microelectronics, Proceedings, 2005, : 75 - 81
  • [7] Synthesis of a super broadband model for on-chip spiral inductors
    Horng, TS
    Jau, JK
    Huang, CH
    Han, FY
    [J]. 2004 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2004, : 453 - 456
  • [8] On-Chip Spiral Inductors and On-Chip Spiral Transistors for Accurate Numerical Modeling
    Dhamodaran, M.
    Kumar, R. Praveen
    Jegadeesan, S.
    [J]. JOURNAL OF MAGNETICS, 2018, 23 (01) : 50 - 54
  • [9] An optimized model of skin effect for on-chip spiral inductors
    Sun, X
    Carchon, G
    De Raedt, W
    [J]. 2004 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2004, : 445 - 448
  • [10] Modeling of Rectangular On-Chip Spiral Inductors
    Sathyasree, J.
    Vanukuru, Venkata
    Nair, Deleep
    Chakravorty, Anjan
    [J]. 2016 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC2016), 2016,
12345