A simplified distribution parasitic capacitance model for on-chip spiral inductors

被引：0
|
作者：
Masuda, T [1 ]
Kodama, A
Nakamura, T
Shiramizu, N
Wada, S
Hashimoto, T
Washio, K
机构：
[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo 1858601, Japan
[2] Renesas Northern Japan Semicond, Tokyo, Japan
[3] Hitachi Ltd, Micro Device Div, Tokyo, Japan
来源：
2006 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS, DIGEST OF PAPERS | 2006年
关键词：
spiral inductor; equivalent circuit model; parasitic capacitance; silicon substrate;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A modeling methodology for determining simply distributed parasitic capacitances used in a lumped equivalent circuit of silicon monolithic spiral inductors is proposed. To calculate the capacitances for the obtained model, the degeneration factors for the total amount of distributed parasitic-capacitances are introduced. A Q-factor modeling-error of less than 9.4% was obtained by comparing the measured and modeled characteristics in the microwave region.
引用
收藏
页码：111 / +
页数：2
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