Machine-Learning Based Congestion Estimation for Modern FPGAs

被引：27

作者：

Maarouf, D. ^{[1
]}

Alhyari, A. ^{[1
]}

Abuowaimer, Z. ^{[1
]}

Martin, T. ^{[1
]}

Gunter, A. ^{[1
]}

Grewal, G. ^{[1
]}

Areibi, S. ^{[1
]}

Vannelli, A. ^{[1
]}

机构：

[1] Univ Guelph, Sch Comp Sci, Sch Engn, Guelph, ON, Canada

来源：

2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) | 2018年

关键词：

FPGA; Congestion; Machine Learning;

D O I：

10.1109/FPL.2018.00079

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Avoiding congestion for routing resources has become one of the most important placement objectives. In this paper, we present a machine-learning model for accurately and efficiently estimating congestion during FPGA placement. Compared with the state-of-the-art machine learning congestion-estimation model, our results show a 25% improvement in prediction accuracy. This makes our model competitive with congestion estimates produced using a global router. However, our model runs, on average, 291x faster than the global router.

引用

页码：427 / 434

页数：8

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