Area and power efficient hard multiple generator for radix-8 modulo 2n-1 multiplier

被引：2

作者：

Kabra, Naveen Kr ^{[1
]}

Patel, Zuber M. ^{[1
]}

机构：

[1] Sardar Vallabhbhai Natl Inst Technol, Elect Engn Dept, Surat 395007, India

来源：

INTEGRATION-THE VLSI JOURNAL | 2020年 / 75卷

关键词：

Low power; Modulo multiplier; RNS; Area efficient; Hard multiple generator; VLSI IMPLEMENTATION;

D O I：

10.1016/j.vlsi.2020.06.009

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we introduce an area and power efficient algorithm to design a hard multiple generator for radix-8 modulo 2(n) - 1 multiplier, which is based on parallel prefix computation of carry propagate. Only odd carry is used to generate hard multiple bits. The proposed architecture uses [log(2)n]-2 prefix level with n/2 prefix operators. The Post-synthesis result of proposed architecture shows 27.91%-36.89%, 9.64%-22.45% and 0.02%-88.62% of saving in area, power and PDP, respectively while post-layout result shows 27.66%-36.88%,14.45%-33.53% and 11.40%-81.11% of saving in area, power and PDP, respectively.

引用

页码：102 / 113

页数：12

共 48 条

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[28] Power-delay-area efficient modulo 2n+1 adder architecture for RNS
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