Design and simulation of hybrid CMOS-SET circuits

被引：24

作者：

Jana, Anindya ^{[1
]}

Singh, N. Basanta ^{[2
]}

Sing, J. K. ^{[3
]}

Sarkar, Subir Kumar ^{[1
]}

机构：

[1] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata 700032, India

[2] Manipur Inst Technol, Dept Elect & Commun Engn, Imphal 795004, Manipur, India

[3] Jadavpur Univ, Dept Comp Sci & Engn, Kolkata 700032, India

来源：

MICROELECTRONICS RELIABILITY | 2013年 / 53卷 / 04期

关键词：

MULTIPLE-VALUED LOGIC; SINGLE-ELECTRON; MEMORY;

D O I：

10.1016/j.microrel.2012.11.001

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Single electron devices have extremely poor driving capabilities so that direct application to practical circuits is as yet almost impossible. A new methodology to overcome this problem is to build hybrid circuits consisting of single electron transistors (SETS) and CMOS interfaces. In this work a room temperature operable hybrid CMOS-SET inverter circuit, hybrid CMOS-SET NOR gate and their Voltage Transfer Characteristics (VTCs) are proposed. The MIB compact model for SET device and BSIM4.6.1 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment. Based on the hybrid CMOS-SET inverter, other logic gates such as NAND, NOR, AND, OR, XOR and XNOR are proposed. All the circuits are verified by means of T-Spice simulation software. (C) 2012 Elsevier Ltd. All rights reserved.

引用

页码：592 / 599

页数：8

共 50 条

[21] A UNIVERSAL TEST SET FOR CMOS CIRCUITS
GUPTA, G
JHA, NK
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1988, 7 (05) : 590 - 597
[22] Design and simulation of hybrid SET-CMOS logic inverter using macro-model technique
El Kazdir, M. S.
Rzaizi, M.
El Assali, K.
Abouelaoualim, D.
REVISTA MEXICANA DE FISICA, 2022, 68 (06)
[23] Hybrid CMOS/Memristor Circuits
Strukov, D. B.
Stewart, D. R.
Borghetti, J.
Li, X.
Pickett, M.
Ribeiro, G. Medeiros
Robinett, W.
Snider, G.
Strachan, J. P.
Wu, W.
Xia, Q.
Yang, J. Joshua
Williams, R. S.
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 1967 - 1970
[24] Design and implementation of SET-CMOS hybrid half subtractor
Ghosh, Arpita
Jain, Amit
Singh, N. B.
Sarkar, Subir Kumar
2014 ANNUAL IEEE INDIA CONFERENCE (INDICON), 2014,
[25] Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation
Barla, Prashanth
Shivarama, Hemalatha
Deepa, Ganesan
Ujjwal, Ujjwal
JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS, 2024, 14 (01)
[26] Hybrid CMOS/nanoelectronic digital circuits: Devices, architectures, and design automation
DeHon, A
Likharev, KK
ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2005, : 375 - 382
[27] Hybrid evolutionary approach to optimal design of CMOS LNA integrated circuits
Li, Yiming
Chou, Hung-Mu
Advances in Computational Methods in Sciences and Engineering 2005, Vols 4 A & 4 B, 2005, 4A-4B : 1088 - 1091
[28] Realistic single-electron transistor modeling and novel CMOS/SET hybrid circuits
Song, KW
Baek, G
Lee, SH
Kim, DH
Kim, KR
Woo, DS
Sim, JS
Lee, JD
Park, BG
2003 THIRD IEEE CONFERENCE ON NANOTECHNOLOGY, VOLS ONE AND TWO, PROCEEDINGS, 2003, : 119 - 121
[29] Bridging the gap between design and simulation of low voltage CMOS circuits
Adornes, Cristina Missel
Alves Neto, Deni Germano
Schneider, Marcio Cherem
Galup-Montoro, Carlos
2021 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), 2021,
[30] Design of CMOS Circuits for Electrophysiology
Van Helleputte, Nick
Mora-Lopez, Carolina
Van Hoof, Chris
IEICE TRANSACTIONS ON ELECTRONICS, 2023, E106C (10) : 506 - 515

← 1 2 3 4 5 →