Multi-Core Architecture for Video Decoding

被引：0

作者：

Lee, Jae-Jin ^{[1
]}

Byun, KyungJin ^{[1
]}

Eum, NakWoong ^{[1
]}

机构：

[1] Elect & Telecommun Res Inst, Multimedia Processor Res Team, Daejeon, South Korea

来源：

2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2012年

关键词：

Multimedia Processor; Multi-Core; Video Decoding; H.264; DESIGN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Multiple international video standards in the market have been developed successfully for many commercial products. This paper proposes a new multimedia core and multi-core architecture for multi-standard video decoding. The proposed multimedia core is based on the 6-stage pipelined dual issue VLIW+SIMD architecture and efficient instructions for video decoding. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. The multi-core architecture consisting of eight multimedia cores is efficient for parallel decoding of various video compression formats including MPEG-2, MPEG-4, AVS and H.264/AVC.

引用

页码：25 / 28

页数：4

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