Noise suppression in VLSI circuits using dummy metal fill

被引:0
|
作者
Gaskill, Steven [1 ]
Shilimkar, Vikas [1 ]
Weisshaar, Andreas [1 ]
机构
[1] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Modem IC processes require metal fill patterning to achieve global uniformity of the metallization/oxide layers. Electrically these fills are often viewed as parasitics to be minimized. In this paper we actively use metal fill to suppress crosstalk noise between coupled traces by selectively grounding metal fills. However, the tradeoff of this improvement is higher total capacitance leading to increased interconnect delay times. We propose design rules that optimize this tradeoff between crosstalk and delay. The design parameters considered include placement of grounded fills, buffer distance and fill shapes. We show that it is best to start grounding metal fills farthest away from the signal traces.
引用
收藏
页码:249 / 252
页数:4
相关论文
共 50 条
  • [41] Switching noise reduction in clock distribution in mixed-mode VLSI circuits
    Parra, P
    Acosta, AJ
    Valencia, M
    VLSI CIRCUITS AND SYSTEMS, 2003, 5117 : 564 - 573
  • [42] Modelling of circuits and systems using PNs with applications to test generation for VLSI circuits
    Kadim, HJ
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 1155 - 1158
  • [43] DESIGN OF RELIABLE VLSI CIRCUITS USING SIMULATION TECHNIQUES
    HSU, WJ
    SHEU, BJ
    GOWDA, SM
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (03) : 452 - 457
  • [44] Implementation of motoneuronal behavior using analog VLSI circuits
    Hudson, TA
    DeWeerth, SP
    42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1999, : 145 - 148
  • [45] IMPLEMENTING NEURAL ARCHITECTURES USING ANALOG VLSI CIRCUITS
    MAHER, MAC
    DEWEERTH, SP
    MAHOWALD, MA
    MEAD, CA
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (05): : 643 - 652
  • [46] Analog Layout Density Uniformity Improvement using Interconnect Widening and Dummy Fill Insertion
    Shomalnasab, Gholamreza
    Zhang, Lihong
    2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017,
  • [47] Physics-based wideband predictive compact model for inductors with high amounts of dummy metal fill
    Tiemeijer, Luuk F.
    Havens, Ramon J.
    Bouttement, Yann
    Pranger, Henk Jan
    IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2006, 54 (08) : 3378 - 3386
  • [48] Improving Copper CMP Topography by Dummy Metal Fill Co-Optimizing Electroplating and CMP Planarization
    Chang, Li-Fu
    Fan, Zhong
    Lu, Daniel
    Bao, Alex
    DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION IV, 2010, 7641
  • [49] SUPPRESSION OF QUANTUM PARTITION NOISE IN MESOSCOPIC ELECTRON BRANCHING CIRCUITS
    LIU, RC
    YAMAMOTO, Y
    PHYSICAL REVIEW B, 1994, 49 (15): : 10520 - 10532
  • [50] GENERALIZED EFFECT OF DYNAMIC SUPPRESSION OF NOISE FOR THE RESONANCE MEASURING CIRCUITS
    GUSEV, AV
    RUDENKO, VN
    VESTNIK MOSKOVSKOGO UNIVERSITETA SERIYA 3 FIZIKA ASTRONOMIYA, 1988, 29 (06): : 13 - 16