共 50 条
- [33] Sub-100-nm Gate-Length Scaling of Vertical InAs/InGaAs Nanowire MOSFETs on Si 2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2017,
- [34] TCAD modeling and simulation of sub-100nm gate length silicon and GaN based SOI MOSFETs TRANSISTOR SCALING- METHODS, MATERIALS AND MODELING, 2006, 913 : 191 - +
- [35] Gate Length Engineering Impact of Sub-10 nm GaN-Based DG-MOSFETs 2017 IEEE INTERNATIONAL WIE CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (IEEE WIECON-ECE 2017), 2017, : 117 - 120
- [37] Performance limitation of sub-100-nm intrinsic-channel double-gate SOI MOSFETs 2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2002, : 60 - 61