Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

被引:35
|
作者
Gaillardon, Pierre-Emmanuel [1 ]
Sacchetto, Davide [2 ]
Beneventi, Giovanni Betti [3 ]
Ben Jamaa, M. Haykel [3 ]
Perniola, Luca [3 ]
Clermidy, Fabien [3 ]
O'Connor, Ian [4 ,5 ]
De Micheli, Giovanni [1 ]
机构
[1] Ecole Polytech Fed Lausanne, Lab Syst Integrat, CH-1015 Lausanne, Switzerland
[2] Ecole Polytech Fed Lausanne, Lab MicroElect Syst, CH-1015 Lausanne, Switzerland
[3] Commissariat Energie Atom & Energies Alternat, F-38054 Grenoble, France
[4] Ecole Cent Lyon, F-69134 Ecully, France
[5] Ecole Polytech, Montreal, PQ H3T 1J4, Canada
基金
欧洲研究理事会;
关键词
3-D integration; nonvolatile memory; oxide memory; phase-change memory; programmable logic arrays; RRAM;
D O I
10.1109/TNANO.2012.2226747
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Emerging nonvolatile memories (ENVMs) such as phase-change random access memories (PCRAMs) or oxide-based resistive random access memories (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of building blocks for field-programmable gate arrays (FPGAs) using ENVMs. We propose an ENVM-based configuration point, a look-up table structure with reduced programming complexity and a high-performance switchbox arrangement. We show that these blocks yield an improvement in area and write time of up to 3x and 33x, respectively, versus a regular Flash implementation. By integrating the designed blocks in an FPGA, we demonstrate an area and delay reduction of up to 28% and 34%, respectively, on a set of benchmark circuits. These reductions are due to the ENVM 3-D integration and to their low on-resistance state value. Finally, we survey many flavors of the technologies and we show that the best results in terms of area and delay are obtained with Pt/TiO2/Pt stack, while the lowest leakage power is achieved by InGeTe stack.
引用
收藏
页码:40 / 50
页数:11
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