A 10-bit 400-MS/s Current-Steering DAC with Process Calibration

被引：0

作者：

Lee, Tzung-Je ^{[1
]}

Chang, Chia-Ming ^{[2
]}

Sung, Tzu-Chiao ^{[2
]}

Wang, Chua-Chin ^{[2
]}

机构：

[1] Cheng Shiu Univ, Dept Comp Sci & Informat Engn, Kaohsiung 83347, Taiwan

[2] Natl Sun Yat Sen Univ, Dept Elect Engn, Kaohsiung 80424, Taiwan

来源：

2013 IEEE INTERNATIONAL CONFERENCE ON CIRCUITS AND SYSTEMS (ICCAS 2013) | 2013年

关键词：

current-steering; digital-to-analog converter; process calibration; nonlinearity;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 10-bit 400-MS/s current-steering DAC is proposed in this paper. A proposed process detector, and a current calibration circuit are used in the binary current cells to calibrate the current error due to the process variation. Besides, an auxiliary delay circuit is employed in the current cell to turn off the additional calibration current. The proposed DAC is implemented using a typical 0.18 mu m 1P6M CMOS process. With the proposed process calibration circuit and delay compensation, the design complexity and core area is dramatically reduced. The core area is 0.29 x 0.20 mm(2). Besides, the worst DNL and INL of the DAC are simulated to be 0.18 LSB and 0.32 LSB, respectively. The power consumption is 3.7 mW.

引用

页码：23 / 26

页数：4

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