Data-reuse and parallel embedded architectures for low-power, real-time multimedia applications

被引：0
|
作者：
Soudris, D [1 ]
Zervas, ND
Argyriou, A
Dasygenis, M
Tatas, K
Goutis, CE
Thanailakis, A
机构：
[1] Democritus Univ Thrace, Dept Elect & Comp Eng, VLSI Design & Testing Ctr, Xanthi 67100, Greece
[2] Univ Patras, Dept Elect & Comp Eng, VLSI Design Lab, Rion 26500, Greece
来源：
INTEGRATED CIRCUIT DESIGN, PROCEEDINGS: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2000年 / 1918卷
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, especially for data-intensive applications. The effect of the data-reuse decisions on the power dissipation but also on area and performance of multimedia applications realized on multiple embedded cores is explored. The interaction between the data-reuse decisions and the selection of a certain data-memory architecture model is also studied, As demonstrator a widely-used video processing algorithmic kernel, namely the full search motion estimation kernel, is used. Experimental results prove that improvements in both power and performance can be acquired, when the right combination of data memory architecture model and data-reuse transformation is selected.
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收藏
页码：243 / 254
页数：12
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